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19-0282; Rev 0; 7/94
K ATION EVALU BLE AVAILA
IT
250Msps, 8-Bit ADC with Track/Hold
____________________________Features
o o o o o o o o o o o o 250Msps Conversion Rate 6.8 Effective Bits at 125MHz Less than 1/2LSB INL 50 Differential or Single-Ended Inputs 270mV Input Signal Range Reference Sense Inputs Ratiometric Reference Inputs Configurable Dual-Output Data Paths Latched, ECL-Compatible Outputs Low Error Rate, Less than 10-15 Metastable States Selectable On-Chip 8:16 Demultiplexer 84-Pin Ceramic Flat Pack
_______________General Description
The MAX100 ECL-compatible, 250Msps, 8-bit analog-todigital converter (ADC) allows accurate digitizing of analog signals from DC to 125MHz (Nyquist frequency). Designed with Maxim's proprietary advanced bipolar processes, the MAX100 contains a high-performance track/hold (T/H) amplifier and a quantizer in a single ceramic strip-line package. The innovative design of the internal T/H assures an exceptionally wide input bandwidth of 1.2GHz and aperture delay uncertainty of less than 2ps, resulting in a high 6.8 effective bits performance. Special comparator output design and decoding circuitry reduce out-of-sequence code errors. The probability of erroneous codes occurring due to metastable states is reduced to less than 1 error per 1015 clock cycles. Unlike other ADCs, which can have errors that result in false full-scale or zero-scale outputs, the MAX100 keeps the magnitude to less than 1LSB. The analog input is designed for either differential or singleended use with a 270mV range. Sense pins for the reference input allow full-scale calibration of the input range or facilitate ratiometric use. Midpoint tap for the reference string is available for applications that need to modify the output coding for a user-defined bilinear response. Use of separate high-current and low-current ground pins provides better noise immunity and highest device accuracy. Dual output data paths provide several data output modes for easy interfacing. These modes can be configured as either one or two identical latched ECL outputs. An 8:16 demultiplexer mode that reduces the output data rates to one-half the clock rate is also available. For applications that require faster data rates, refer to Maxim's MAX101, which allows conversion rates up to 500Msps.
MAX100
________________________Applications
High-Speed Digital Instrumentation High-Speed Signal Processing Medical Systems Radar/Sonar High-Energy Physics Communications
______________Ordering Information
PART TEMP. RANGE PIN-PACKAGE 84 Ceramic Flat Pack (with heatsink) MAX100CFR* 0C to +70C
*Contact factory for 84-Pin Ceramic Flat Pack without heatsink.
_________________________________________________________Functional Diagram
VART VARTS VACT VACTS VARBS VARB L A T C H E S B U F F E R L A T C H E S
8 AIN+ AINCLK CLK TRACK/ HOLD MODE CONTROL FLASH CONVERTER
8
AData (A0-A7) DCLK DCLK
8
MOD
DIV
A=B
BData (B0-B7)
________________________________________________________________ Maxim Integrated Products
1
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250Msps, 8-Bit ADC with Track/Hold MAX100
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltages VCC .............................................................................0V to +7V VEE ...............................................................................-7V to 0V VCC - VEE............................................................................+12V Analog Input Voltage .............................................................2V Digital Input Voltage .................................................-2.3V to +0V Reference Voltage (VART) .....................................-0.3V to +1.5V Reference Voltage (VARB).....................................-1.5V to +0.3V Data Output Current ..........................................................-33mA DCLK Output Current ........................................................-43mA Operating Temperature Range...............................0C to +70C Operating Junction Temperature (Note 2)............0C to +125C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10sec) .............................+250C
Note 1: The digital control inputs are diode protected; however, permanent damage may occur on unconnected units under highenergy electrostatic fields. Keep unused units in conductive foam or shunt the terminals together. Discharge the conductive foam to the destination socket before insertion. Note 2: Typical thermal resistance, junction-to-case RJC = 5C/W and thermal resistance, junction to ambient (MAX100CA) RJA = 12C/W, providing 200 lineal ft/min airflow with heatsink. See Package Information.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VEE = -5.2V, VCC = +5V, RL = 50 to -2V, VART = 1.02V, VARB = -1.02V, TMIN to TMAX = 0C to +70C, TA = +25C, unless otherwise noted.) (Note 3) PARAMETER ACCURACY Resolution Integral Nonlinearity (Note 4) Differential Nonlinearity DYNAMIC SPECIFICATIONS Effective Bits ENOB fCLK = 250MHz, VIN = 95% full scale (Note 5) fAIN = 10MHz fAIN = 50MHz fAIN = 125MHz 7.4 7.1 6.8 44.5 250 1.2 270 2 230 -305 -17 1.8 49 0.008 315 -215 +32 2.5 51 dB Msps GHz ps ps Bits INL DNL AData, BData AData, BData, no missing codes TA = +25C TA = TMIN to TMAX TA = +25C TA = TMIN to TMAX 8 0.5 0.6 0.75 0.85 Bits LSB LSB SYMBOL CONDITIONS MIN TYP MAX UNITS
Signal-to-Noise Ratio Maximum Conversion Rate Analog Input Bandwidth Aperture Width Aperture Jitter ANALOG INPUT Input Voltage Range Input Offset Voltage Least-Significant-Bit Size Input Resistance Input Resistance Temperature Coefficient
SNR fCLK BW3dB tAW tAJ
fAIN = 50MHz, fCLK = 250MHz, VIN = 95% full scale (Note 6) (Note 7) Figure 5 Figure 5 Full scale Zero scale AIN+, AIN-, TA = TMIN to TMAX TA = TMIN to TMAX AIN+ and AIN- with respect to GND AIN+ to AIN-, Table 2, TA = TMIN to TMAX
VIN VIO LSB RI
mV mV mV /C
2
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250Msps, 8-Bit ADC with Track/Hold
ELECTRICAL CHARACTERISTICS (continued)
(VEE = -5.2V, VCC = +5V, RL = 50 to -2V, VART = 1.02V, VARB = -1.02V, TMIN to TMAX = 0C to +70C, TA = +25C, unless otherwise noted.) (Note 3) PARAMETER REFERENCE INPUT Reference String Resistance Reference String Resistance Temperature Coefficient LOGIC INPUTS Digital Input Low Voltage (Note 8) Digital Input High Voltage (Note 8) VIL VIH DIV, MOD, A=B, CLK, CLK, TA = TMIN to TMAX DIV, MOD, A=B, CLK, CLK, TA = TMIN to TMAX DIV, MOD, A=B = -1.8V, TA = TMIN to TMAX Digital Input Low Current IIL CLK, CLK, VIL = -1.8V (no termination), TA = TMIN to TMAX DIV, MOD, A=B = -0.8V, TA = TMIN to TMAX Digital Input High Current IIH CLK, CLK, VIH = -0.8V (no termination), TA = TMIN to TMAX AData, BData, DCLK, DCLK AData, BData, DCLK, DCLK TA = +25C TA = TMIN to TMAX TA = +25C TA = TMIN to TMAX TA = +25C TA = TMIN to TMAX TA = +25C TA = TMIN to TMAX TA = TMIN to TMAX VCC(nom) = 0.25V VEE(nom) = 0.25V -750 -780 35 40 40 -560 -1.07 -5 0 -5 0 20 A 80 20 A 80 -1.5 V V SYMBOL RREF VART to VARB CONDITIONS MIN 116 0.02 TYP MAX 175 UNITS /C
MAX100
LOGIC OUTPUTS (Note 9) Digital Output Low Voltage Digital Output High Voltage POWER REQUIREMENTS Positive Supply Current Negative Supply Current Common-Mode Rejection Ratio Power-Supply Rejection Ratio ICC IEE CMRR PSRR VCC = 5.0V VEE = -5.2V VINCM = 0.5V TA = TMIN to TMAX 464 670 710 mA mA dB dB VOL VOH -1.95 -1.95 -1.02 -1.10 -1.60 -1.50 -0.70 -0.70 V V
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250Msps, 8-Bit ADC with Track/Hold MAX100
TIMING CHARACTERISTICS
(VEE = -5.2V, VCC = +5V, RL = 50 to -2V, VART = 1.02V, VARB = -1.02V, TA = +25C, unless otherwise noted.) PARAMETER Clock Pulse Width Low Clock Pulse Width High CLK to DCLK Propagation Delay DCLK to A/BData Propagation Delay Rise Time Fall Time SYMBOL tPWL tPWH tPD1 tPD2 tR tF CONDITIONS CLK, CLK, Figures 1 and 2 CLK, CLK, Figures 1 and 2 DIV = 0, Figure 1 DIV = 1, Figure 2 DIV = 0, Figure 1 DIV = 1, Figure 2 DCLK 20% to 80% DATA DCLK 20% to 80% DATA See Figures 3 and 4 and Table 1 (delay depends on output mode) Divide-by-1 mode Divide-by- AData 2 mode BData MIN 1.9 1.9 0.8 1.9 0.5 -1.4 500 700 600 550 7 1/2 7 1/2 8 1/2 7 1/2 7 1/2 8 1/2 TYP MAX 5.0 2.4 5.7 2.2 -0.1 UNITS ns ns ns ns ps ps
Pipeline Delay (Latency)
tNPD
Clock Cycles
Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9:
All devices are 100% production tested at +25C and are guaranteed by design for TA = TMIN to TMAX as specified. Deviation from best-fit straight line. See Integral Nonlinearity section. See the Signal-to-Noise Ratio and Effective Bits section in the Definitions of Specifications. SNR calculated from effective bits performance using the following equation: SNR (dB) = 1.76 + (6.02) (effective bits). Clock pulse width minimum requirements tPWL and tPWH must be observed to achieve stated performance. Functionality guaranteed for -1.07 VIH -0.7 and -2.0 VIL -1.5. Outputs terminated through 50 to -2.0V.
__________________________________________Typical Operating Characteristics
(TA = +25C, unless otherwise noted.)
INTEGRAL NONLINEARITY vs. OUTPUT CODE
0.75 0.50 DNL (LSBs) 0.25 INL (LSBs) 0 -0.25 -0.50 -0.75 0 64 128 OUTPUT CODE 192 256 0.75 0.50 0.25 0 -0.25 -0.50 -0.75 0
DIFFERENTIAL NONLINEARITY vs. OUTPUT CODE
64
128 OUTPUT CODE
192
256
4
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250Msps, 8-Bit ADC with Track/Hold
____________________________Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted.) FFT PLOT (fAIN = 120.4462MHz)
0 -10 SIGNAL AMPLITUDE (dB)
SIGNAL AMPLITUDE (dB) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 0 12.5 25 37.5 50 62.5 FREQUENCY (MHz) fCLK = 250MHz, fAIN = 10.4462MHz SER = -45.87dB, NOISE FLOOR = -68.5dB
MAX100
FFT PLOT (fAIN = 10.4462MHz)
-20 -30 -40 -50 -60 -70 -80 -90 -100 0 12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 FREQUENCY (MHz) fCLK = 250MHz, fAIN = 120.4462MHz SER = -42.3dB, NOISE FLOOR = -65.4dB
EFFECTIVE BITS vs. ANALOG INPUT FREQUENCY
MAX100-10
EFFECTIVE BITS vs. CLOCK FREQUENCY
7 6 EFFECTIVE BITS 5 4 3 2 1 0 fAIN = 10.4MHz, VIN = 95% FS
MAX100-11
8 7 6 EFFECTIVE BITS 5 4 3 2 1 0 0 50 100 150 200 250 fCLK = 250MHz, VIN = 95% FS
8
300
0
50
100
150 fCLK (MHz)
200
250 300
fAIN (MHz)
EFFECTIVE BITS vs. ANALOG INPUT FREQUENCY
MAX100-12
EFFECTIVE BITS vs. ANALOG INPUT FREQUENCY
7 6 EFFECTIVE BITS 5 4 3 2 1 0 TCASE = -15C, fCLK = 250MHz VIN = 95% FS 0 50 100 150 200 250
MAX100-13
8 7 6 EFFECTIVE BITS 5 4 3 2 1 0 0 50 100 150 200 TCASE = +80C, fCLK = 250MHz, VIN = 95% FS
8
250
fAIN (MHz)
fAIN (MHz)
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250Msps, 8-Bit ADC with Track/Hold MAX100
____________________________Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted.) CLOCK RELATIONSHIP (DIVIDE-BY-1 MODE) DIGITAL CLOCK (POSITIVE EDGE)
A DCLK 100mV/div
B
A = CLK, 200mV/div B = DCLK, 200mV/div
TIMEBASE = 1ns/div, fCLK = 250MHz
TIMEBASE = 1ns/div, tr = 580ps
CLOCK/DATA (DIVIDE-BY-1 MODE)
A
DATA OUTPUT (NEGATIVE EDGE)
AData OUTPUT B 100mV/div C
A = CLK, 500mV/div B = DCLK, 500mV/div C = AData, 500mV/div
TIMEBASE = 2ns/div, fCLK = 250MHz
TIMEBASE = 1ns/div, tf = 596ps
CLOCK/DATA (DIVIDE-BY-2 MODE)
A
CLOCK/DATA DETAIL (DIVIDE-BY-5 MODE)
A B
C
B
A = CLK, 500mV/div B = DCLK, 500mV/div C = AData, 500mV/div
TIMEBASE = 2ns/div, fCLK = 250MHz
A = DCLK, 200mV/div B = AData, 200mV/div
TIMEBASE = 5ns/div, fCLK = 250MHz
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250Msps, 8-Bit ADC with Track/Hold
______________________________________________________________Pin Description
PIN 1 2, 62 3, 61 4, 7, 15, 49, 57, 60, 64, 67, 70, 71, 74, 77, 78, 79, 82, 84 5, 6, 9, 10, 31, 33, 35, 48, 58, 59, 63, 81, 83 8, 21, 43, 56 11 12 13 14 16 17, 20, 23, 26, 36, 39, 42, 45 19, 22, 25, 28, 38, 41, 44, 47 18, 24, 27, 30, 34, 37, 40, 46 29 32, 69, 80 50 51 NAME PAD CLK CLK Internal connection, leave open. Complementary Differential Clock Inputs. Can be driven from standard 10K ECL with the following considerations: Internally, pins 2 & 62 and 3 & 61 are the ends of a 50 transmission line. Either end can be driven, with the other end terminated with 50 to -2V. See Typical Operating Circuit. FUNCTION
MAX100
GND
Power-Supply Ground. Connect GND and DGND pins (Note 10).
N.C.
No Connect--there is no internal connection to these pins.
VCC DIV MOD DCLK DCLK A=B A7-A0
Positive power supply, +5V 5% nominal Divide Enable Input. DIV and MOD select the output modes. See Table 1. Modulus. MOD and DIV select the output modes. See Table 1. Complementary Differential Clock Outputs. Used to synchronize following circuitry: AData and BData outputs are valid tPD2 after the rising edge of DCLK. See Figures 1-4. Sets AData equal to BData when asserted (A=B = 1). See Table 1.
AData and BData Outputs. A0 and B0 are the LSBs, and A7 and B7 are the MSBs. AData and BData outputs conform to standard 10K ECL logic swings and drive 50 transmission lines. Terminate with 50 to -2V. See Figures 1-4. B7-B0
DGND
Power-Supply Ground. Connect all ground (GND, DGND) pins together, as described in Note 10.
SUB VEE VART VARTS
Circuit Substrate Contact. This pin must be connected to VEE. Negative Power Supply, -5.2V 5% nominal Positive Reference Voltage Input (Note 11) Positive Reference Voltage Sense (Note 11)
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250Msps, 8-Bit ADC with Track/Hold MAX100
_________________________________________________Pin Description (continued)
PIN 52 53 54 55 65 66 68 72, 73 75, 76 Note 10: Note 11: Note 12: NAME VACTS VACT VARBS VARB TP3 TP2 TP1 AIN+ AINFUNCTION Reference Bias Resistor Center-Tap Sense (Note 12) Reference Bias Resistor Center Tap (Note 12) Negative Reference Voltage Sense (Note 11) Negative Reference Voltage Input (Note 11) Internal node. Do not connect. Internal node. Do not connect. Internal connection. This pin must be connected to GND. Analog Inputs, internally terminated with 50 to ground. Full-scale linear input range is approximately 270mV. Drive AIN+ and AIN- differentially for best high-frequency performance.
Use a multilayer board with a separate layer dedicated to ground. Connect GND and DGND in separate areas in the ground plane (separated by at least 1/4 inch) and at only one location on the board (see Typical Operating Circuit). Reference bias supply. Use a separate high-quality supply for these pins. Carefully bypassing these pins to achieve noise-free operation of the reference supplies contributes directly to high ADC accuracy. The center-tap connection of the MAX100 is normally left open. It can be driven with a bias voltage, but should be bypassed carefully (refer to Note 11).
CLK CLK DCLK DCLK
AData
BData tpd1 tpwl tpd2 tpwh
Figure 1. Output Timing: Divide-by-1 Mode (DIV = 0)
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250Msps, 8-Bit ADC with Track/Hold MAX100
CLK CLK DCLK DCLK
AData
BData tpd1 tpd2 tpwl tpwh
Figure 2. Output Timing: Divide-by-2 or Divide-by-5 Mode (DIV = 1)
CLK N-1 N N+1
DCLK
1
2
3
4
5
6
7
8
AData
N-1
N
N+1
BData tpd2 tpd1 tNPD
N-1
N
N+1
Figure 3. Output Timing: Clock to Data, Divide-by-1 Mode (fast mode, DIV = 0)
N-2 CLK 1 DCLK 2 3 4 5 N-1 N N+1 N+2
AData
N-1
N+1
N+3
BData tpd2 tNPD
N-2
N
N+2
Figure 4. Output Timing: Divide-by-2 Mode (DIV = 1)
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250Msps, 8-Bit ADC with Track/Hold MAX100
______Definitions of Specifications
Signal-to-Noise Ratio and Effective Bits
Signal-to-noise ratio (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other analog-to-digital (A/D) output signals. The theoretical minimum A/D noise is caused by quantization error and is a direct result of the ADC's resolution: SNR = (6.02N + 1.76)dB, where N is the number of effective bits of resolution. Therefore, a perfect 8-bit ADC can do no better than 50dB. The FFT plots in the Typical Operating Characteristics show the output level in various spectral bands. Effective bits is calculated from a digital record taken from the ADC under test. The quantization error of the ideal converter equals the total error of the device. In addition to ideal quantization error, other sources of error include all DC and AC nonlinearities, clock and aperture jitter, missing output codes, and noise. Noise on references and supplies also degrades effective bits performance. The ADC's input is a sine wave filtered with an anti-aliasing filter to remove any harmonic content. The digital record taken from this signal is compared against a mathematically generated sine wave. DC offsets, phase, and amplitudes of the mathematical model are adjusted until a best-fit sine wave is found. After subtracting this sine wave from the digital record, the residual error remains. The rms value of the error is applied in the following equation to yield the ADC's effective bits. Effective bits = N - log2
CLK CLK tAW ANALOG INPUT tAD tAJ SAMPLED DATA (T/H)
TRACK T/H
HOLD APERTURE DELAY (tAD) APERTURE WIDTH (tAW) APERTURE JITTER (tAJ)
TRACK
Figure 5. T/H Aperture Timing
(
measured rms error ------------------ ideal rms error
)
typical converters can be incorrect, including false fullor zero-scale output. The MAX100's unique design reduces the magnitude of this type of error to 1LSB, and reduces the probability of the error occurring to less than one in every 10 15 clock cycles. If the MAX100 were operated at 250MHz, 24 hours a day, this would translate to less than one metastable-state error every 46 days.
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the transfer function from a reference line measured in fractions of 1LSB using a "best straight line" determined by a least square curve fit.
where N is the resolution of the converter. In this case, N = 8. The worst-case error for any device will be at the converter's maximum clock rate with the analog input near the Nyquist rate (1/2 the input clock rate).
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between the measured LSB step and an ideal LSB step size between adjacent code transitions. DNL is expressed in LSBs and is calculated using the following equation: [VMEAS - (VMEAS-1)] - LSB DNL(LSB) = -------------------------- LSB where VMEAS-1 is the measured value of the previous code. A DNL specification of less than 1LSB guarantees no missing codes and a monotonic transfer function.
Aperture Width and Jitter
Aperture width is the time the T/H circuit takes to disconnect the hold capacitor from the input circuit (i.e., to turn off the sampling bridge and put the T/H in hold mode). Aperture jitter is the sample-to-sample variation in aperture delay (Figure 5).
Error Rates
Errors resulting from metastable states may occur when the analog input voltage, at the time the sample is taken, falls close to the decision point for any one of the input comparators. The resulting output code for many
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250Msps, 8-Bit ADC with Track/Hold
_______________Detailed Description
Converter Operation
The parallel or "flash" architecture used by the MAX100 provides the fastest multibit conversion of all common integrated ADC designs. The basic element of a flash (as with all other ADC architectures) is the comparator, which has a positive input, a negative input, and an output. If the voltage at the positive input is higher than the negative input (connected to a reference), the output will be high. If the positive input voltage is lower than the reference, the output will be low. A typical nbit flash consists of 2n-1 comparators with negative inputs evenly spaced at 1LSB increments from the bottom to the top of the reference ladder. For n = 8, there will be 255 comparators. For any input voltage, all the comparators with negative inputs connected to the reference ladder below the input voltage will have outputs of 1, and all comparators with negative inputs above the input voltage will have outputs of 0. Decode logic is provided to convert this information into a parallel n-bit digital word (the output) corresponding to the number of LSBs (minus 1) that the input voltage is above the level set at the bottom of the ladder. Finally, the comparators contain latch circuitry and are clocked. This allows the comparators to function as described above when, for example, clock is low. When clock goes high (samples) the comparator will latch and hold its state until the clock goes low again. When CLK goes low, the most recent sample is presented to the ADC's input comparators. Internal processing of the sampled data is delayed for several clock cycles before it is available at outputs AData or BData. All output data is timed with respect to DCLK and DCLK (Figures 1-4).
MAX100
__________Applications Information
Analog Input Ranges
Although the normal operating range is 270mV, the MAX100 can be operated with up to 500mV on each input with respect to ground. This extended input level includes the analog signal and any DC common-mode voltage. To obtain a full-scale digital output with differential input drive, a nominal +270mV must be applied between AIN+ and AIN-. That is, AIN+ = +135mV and AIN- = -135mV (with no DC offset). Mid-scale digital output code occurs when there is no voltage difference across the analog inputs. Zero-scale digital output code, with differential -270mV drive, occurs when AIN+ = -135mV and AIN- = +135mV. Table 2 shows how the output of the converter stays at all ones (full scale) when over ranged or all zeros (zero scale) when under ranged. For single-ended operation: 1) Apply a DC offset to one of the analog inputs, or leave one input open. (Both AIN+ and AIN- are terminated internally with 50 to analog ground.) 2) Drive the other input with a 270mV + offset to obtain either full- or zero-scale digital output. If a DC common-mode offset is used, the total voltage swing allowed is 500mV (analog signal plus offset with respect to ground).
Track/Hold
As with all ADCs, if the input waveform is changing rapidly during the conversion the effective bits and SNR will decrease. The MAX100 has an internal track/hold (T/H) that increases attainable effective-bits performance and allows more accurate capture of analog data at high conversion rates. The internal T/H circuit provides two important circuit functions for the MAX100: 1) Its nominal voltage gain of 4 reduces the input driving signal to 270mV differential (assuming a 1.02V reference). 2) It provides a differential 50 input that allows easy interface to the MAX100.
Table 1. Input Voltage Range
INPUT AIN+** (mV) +135 0 -135 +270 0 -270 AIN-** (mV) -135 0 +135 0 0 0 OUTPUT CODE 11111111 10000000 00000000 11111111 10000000 00000000 MSB to LSB full scale mid scale zero scale full scale mid scale zero scale
Differential
Single Ended
Data Flow
The MAX100 contains an internal T/H amplifier that stores the analog input voltage for the ADC to convert. The differential inputs AIN+ and AIN- are tracked continuously between data samples. When a negative CLK edge is applied, the T/H enters hold mode (Figure 5).
**An offset VIO, as specified in the DC electrical parameters, may be present at the input. Compensate for this offset by either adjusting the reference voltage (VART or VARB), or introducing an offset voltage in one of the input terminals AIN + or AIN-.
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250Msps, 8-Bit ADC with Track/Hold MAX100
Table 2. Output Mode Control
DIV MOD A=B DCLK* (MHz) MODE DESCRIPTION VART Divide by 1 Data appears on AData only, BData port inactive (Figure 3). AData identical to BData (Figure 3). 8:16 demultiplexer mode. AData and BData ports are active. BData carries older sample and AData carries most recent sample (Figure 4). AData and BData ports are active, both carry identical sampled data. Alternate samples are taken but discarded. AData port updates data on 5th input CLK. BData port inactive. Other 4 sampled data points are discarded. AData and BData ports are both active with identical data. Data is updated on output ports every 5th input clock (CLK). The other 4 samples are discarded.
PARASITIC RESISTANCE POSITIVE REFERENCE
0
X
0
250
VARTS
R
0
X
1
250
Divide by 1
R
TO COMPARATORS
1
0
0
125
Divide by 2
R/2
VACT VACTS
CENTER TAP R/2
1
0
1
125
Divide by 2
1
1
0
50
Divide by 5
R
R
1
1
1
50
Divide by 5
VARBS
PARASITIC RESISTANCE
VARB --- --- *Input clocks (CLK, CLK) = 250MHz for all above combinations. In divide-by-2 or divide-by-5 mode the output clock DCLK will always be a 50% duty-cycle signal. In divide-by-1 mode DCLK will have the same duty cycle as CLK.
NEGATIVE REFERENCE
Figure 6. Reference Ladder String
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250Msps, 8-Bit ADC with Track/Hold
Reference
The ADC's reference resistor is a Kelvin-sensed, centertapped resistor string that sets the ADC's LSB size and dynamic operating range. Normally, the top and bottom of this string are driven with an op amp, and the center tap is left open. However, driving the center tap is an effective way to modify the output coding to provide a user-defined bilinear response. The buffer amplifier used to drive the top and bottom inputs will need to supply approximately 18mA due to the resistor string impedance of 116 minimum. A reference voltage of 1.02V is normally applied to inputs VART and VARB. This reference voltage can be adjusted up to 1.4V to accommodate extended input requirements (accuracy specifications are guaranteed with 1.02V references). The reference input VARTS, VARBS, and VACTS allow Kelvin sensing of the applied voltages to increase precision. An RC network at the ADC's reference terminals is needed for best performance. This network consists of a 33 resistor connected in series with the op amp output that drives the reference. A 0.47F capacitor must be connected near the resistor at the op amp's output (see Typical Operating Circuit). This resistor and capacitor combination should be located within 0.5 inches of the MAX100 package. Any noise on these pins will directly affect the code uncertainty and degrade the ADC's effective-bits performance. DCLK and DCLK are output clock signals derived from the input clocks and are used for external timing of the AData and BData outputs. The MAX100 is characterized to work with maximum input clock frequencies of 250MHz (Table 1). See Typical Operating Circuit.
MAX100
Output Mode Control
DIV, MOD, and A=B are input pins that determine the operating mode of the two output data paths. Six options are available (Table 1). A typical operating configuration (8:16 demultiplexer mode) is set by 1 on DIV, 0 on MOD, and 0 on A=B. This will give the most recent sample at AData with the older data on BData. Both outputs are synchronous and are at half the input clock rate. To terminate the control inputs, use a resistor to -2V or the equivalent circuit resistor combination from DGND to -5.2V up to 1k. When using a diode pull-up to tie an input high, bias the diode "on" with a pull-down resistor to avoid input voltage excursions close to ground. The control inputs are compatible with standard ECL 10K logic levels over temperature.
Layout, Grounding, and Power Supplies
The MAX100 is designed with separate analog and digital ground connections to isolate high-current digital noise spikes. The high-current digital ground, DGND, is connected to the collectors of the output emitter follower transistors. The low-current ground connection is GND, which is a combination of the analog ground and the ground of the low-current digital decode section. The DGND and GND connections should be at the same DC level, and should be connected at only one location on the board. This will provide better noise immunity and highest device accuracy. A ground plane is recommended. A +5V 5% supply as well as a -5.2V 5% supply is needed for proper operation. Bypass the VEE and VCC supply pins to GND with high-quality 0.1F and 0.001F ceramic capacitors located as close to the package as possible. An evaluation kit with a suggested layout is available.
CLK and DCLK
All input and output clock signals are differential. The input clocks, CLK and CLK, are the primary timing signals for the MAX100. CLK and CLK are fed to the internal circuitry from pins 2 & 3 or pins 62 & 61 through an internal 50 transmission line. One pair of CLK/CLK inputs should be driven and the other pair terminated by 50 to -2V. Either pair can be used as the driven inputs (input lines are balanced) for easy circuit connection. A minimum pulse width (tPWL) is required for CLK and CLK (Figures 1-4). For best performance and consistent results, use a low phase-jitter clock source for CLK and CLK. Phase jitter larger than 2ps from the input clock source reduces the converter's effective-bits performance and causes inconsistent results.
______________________________________________________________________________________
13
250Msps, 8-Bit ADC with Track/Hold MAX100
___________________________________________________Typical Operating Circuit
0.01F 1 +VS VOUT GND 3 MX580LH 2 0.01F 150 1.02V 0.001F 2.5V +5V
0.1F
50
1/2 MAX412
20 50 50
8, 21, 43, 56 VART VCC
MC100E151
D > 8 Q Q
120 51
0.22F
CMPSH-3
51
VARTS VACT VACTS
AData
D >
Q Q
20k 20k 50k
51
54
MC100E151
VARBS D > VARB 8 BData D > Q Q Q Q
1/2 MAX412
20 33 55
0.22F 70k 10k
CMPSH-3
MAX100
WATKINS-JOHNSON SMRA 89-1
0.47F 72. 73 AIN+ DCLK DCLK 75, 76 AINA=B 16 50 -2V CLOCK
14 13
1k -2V 1k
2 50 -2V 62 CLK DIV 3 11
-2V
MC100E116
-2V
50
CLK 61 DGND * GND
MOD
12
1k -2V
SUB VEE 29 32, 69, 80 0.1F -5.2V 0.001F 10F
*PINS 68, 4, 7, 15, 49, 57, 60, 64 67, 70, 71, 74, 77, 78, 79, 82, 84, 18, 24, 27, 30, 34, 37, 40, 46
14
______________________________________________________________________________________
250Msps, 8-Bit ADC with Track/Hold
____________________________________________________________Pin Configuration
MAX100
TOP VIEW
GND
GND
GND
AIN+
GND
GND
AIN+
GND
GND
GND
GND
AIN-
AIN-
N.C.
N.C.
VEE
84
83
82
81
80
VEE
79
78
77
76
75
74
73
72
71
70
69
68
TP1
67
66
65
64 63 N.C. 62 CLK 61 CLK 60 GND 59 58 57 56 55 N.C. N.C. GND VCC VARB VARBS 54 53 VA CT 52 VA CTS 51 VARTS 50 VART 49 48 47 46 45 44 43 GND N.C. B0 DGND A0 B1 VCC A1 42
PAD CLK CLK GND N.C. N.C. GND VCC N.C. N.C. DIV MOD DCLK DCLK GND A=B A7 DGND B7 A6 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 24 25 26 27 28 29 30 31 32 33 35 36 37 38 40 22 34 23 39 41 B2
MAX100
DGND
DGND
DGND
DGND
Ceramic Flat Pack
______________________________________________________________________________________
DGND
DGND
N.C.
B3
SUB
N.C.
N.C.
VEE
A3
A2
B6
A5
B5
A4
B4
GND
TP2
TP3
15
250Msps, 8-Bit ADC with Track/Hold MAX100
________________________________________________________Package Information
PIN FIN HEATSINK FORCED CONVECTION PARAMETERS
21 19 JA (C/W) 17 15 0 Degrees* 13 11 45 Degrees* 12 7 0 100 200 300 400 500 VELOCITY (ft /min) *DIRECTION OF AIRFLOW ACROSS HEATSINK
MAX100-insertB
23
E1 E E2 e
DIM S 0.060.005(7x)
D1 D D2 D3
PIN #1 c b A2 A1
0.075.020(6x) EQUAL SPACES
MILLIMETERS MIN MAX A 17.272 18.288 A1 1.041 1.270 A2 3.048 3.302 b 0.406 0.508 C 0.228 0.279 D 29.184 29.794 D1 44.196 44.704 D2 25.298 25.502 D3 28.448 28.829 1.270 BSC e E 29.184 29.794 E1 44.196 44.704 E2 25.298 25.502 E3 28.194 28.702 S 1.930 2.184
INCHES MIN MAX 0.680 0.720 0.041 0.050 0.120 0.130 0.016 0.020 0.009 0.011 1.149 1.173 1.740 1.760 0.996 1.004 1.120 1.135 0.050 BSC 1.149 1.173 1.740 1.760 0.996 1.004 1.110 1.130 0.076 0.086
A 5-6 E3
84 LEAD CERAMIC FLAT PACK WITH HEAT SINK
0.060.005
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 (c) 1994 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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